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This year’s Design and Verification Conference and Exhibition (DVCon Europe) takes place on October 24 and 25 (2018). DVCon Europe has turned into the best conference for virtual platform topics, and this year is no exception. There are some good talks coming!
I will be talking about temporal decoupling in virtual platforms – a topic that I have written about from time to time. It was time to document a bit more what happens and how the use of temporal decoupling impacts software behavior. A longer teaser about what I am going to talk about is found on my Intel blog, at https://software.intel.com/en-us/blogs/2018/10/10/intel-talks-at-dvcon-europe
A couple of Intel colleagues will also be presenting:
- Evgeny Yulyugin will present his work on optimizing direct execution-based virtual platform instruction-set simulation in the presence of complicated instructions
- Roman Popov will talk about hardware construction (algorithmic circuit generation) in synthesizable SystemC. Not about virtual platforms directly, but still somewhat related.
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